This invention relates generally to analog-to-digital converters, and in particular to a multiple-slope integrating analog-to-digital converter having increased linearity.
Conventional multiple-slope integrating analog-to-digital converters (ADCs) have been developed because of the long time periods and perhaps relatively high voltage headroom required to charge and discharge the integrating capacitor in a dual-slope integrating ADC. In multiple slope integrating ADCs, quantities of charge are periodically removed or added (represented by slopes of known polarity and duration) during the integrate, or charge cycle (also known as the run-up cycle) so that an unknown input voltage is never large enough to saturate the integrator, and a relatively small charge remains on the integrating capacitor to be discharged during the de-integrate, or discharge cycle (also known as the run-down cycle). The charge removed or added during the integrate cycle is kept track of by counting slopes which represent the known quantities of charge removed or added, and accounted for in making the final determination of the value of the unknown voltage. The multiple slope techniques may also be applied during the de-integrate or run-down cycle to shorten the amount of time required to discharge the integrator capacitor, resulting an ADC with increased sensitivity and speed. Examples of multiple slope integrating ADCs are taught in U.S. Pat. No. 4,357,600 to Ressemeyer et al. and U.S. Pat. No. 5,321,403 to Eng et al.
Many of the problems associated with prior art multiple slope integrating ADCs stem from the large number of high-speed switching operations that occur in a short period of time, particularly during the integrate cycle. Prior art investigators found that by keeping the number of switching transitions constant for all measurements, and by alternating the condition of switches connecting positive and negative reference voltages to the integrator in a both on, both off sequence, non-linearities due to switch current injection could be minimized. Such switching operations result in a comparatively slow ADC, e.g. about six readings per second for an 81/2-digit display.